Hybrid Polariton Device Promises Low-Energy AI Chips
Researchers at the University of Pennsylvania built a hybrid light-matter quasiparticle, called a polariton, that replaces selected electronic gates with photonic operations. The device performed matrix multiplications at 10 times the speed of conventional silicon while drawing 90 percent less power in benchmark tests. Fabrication used standard CMOS processes plus a thin-film perovskite layer.
This work shows that replacing selected arithmetic units with optical components can cut both latency and energy per inference. Readers should audit their model-serving pipeline for matrix-heavy stages that could migrate to photonic accelerators once the hardware reaches commercial boards.
The Penn electrical-engineering group led by Professor Ritesh Agarwal has taped out a 64-by-64 polariton array that sustains 1.2 tera-operations per second at 35 femtojoules per operation on MNIST inference.
Step 1: Visit the open-source repository at https://github.com/PennPolariton/polariton-sim and clone the simulation scripts. Step 2: Run the provided Jupyter notebook that models a single polariton gate against a PyTorch linear layer on the same input tensor. Step 3: Compare the recorded energy and latency values; expect roughly a 10x throughput gain and 90 percent lower joules per inference on the photonic path.