Vertical stacking removes the memory wall in AI chips
Engineers at imec and CEA-Leti bonded a 16-layer memory tier directly atop a logic tier using hybrid copper-to-copper vias 300 nm in diameter. The 3D path cuts average data-travel distance from 2 mm to 40 µm, raising effective bandwidth to 4 TB/s while lowering access energy to 0.3 pJ/bit. A prototype ResNet-50 inference run completed in 11 ms at 185 mW.
You reconsider the flat PCB as the default layout. Instead, you model data motion cost first and ask whether a vertical memory layer would shrink both time and joules in your training loop. The exercise changes procurement specs from 'more HBM' to 'acceptable thermal density for 3D stacking.'
The CEA-Leti 3D integration team delivered a 64 mm² test chip to Samsung Foundry; the device sustained 2.1 TOPS/W on MobileNetV3 while keeping junction temperature below 85 °C under continuous load.
Step 1: Download the open-source thermal model at https://github.com/3D-IC-thermal/thermal3d. Step 2: Edit the JSON file 'stack_config.json' and set memory_layers to 8 and via_pitch to 5 µm. Step 3: Execute 'python simulate.py'; the script returns peak temperature and bandwidth numbers you can insert into your own performance spreadsheet.