Penn Researchers Demonstrate Hybrid Light Matter AI Accelerator
University of Pennsylvania physicists built polariton based logic gates that combine photons and excitons. Early devices perform matrix multiplications at 0.3 picojoules per operation, roughly 100 times lower energy than current electronic TPUs. The proof of concept chip was fabricated on a standard III V semiconductor process.
Engineers should consider energy per operation as a first class metric when selecting accelerators. Workflows may move selected inference steps onto emerging photonic hardware once commercial boards appear. Latency sensitive pipelines could gain speed by avoiding repeated electronic optical conversions.
The Penn Excitonics Lab published results in Nature Photonics showing a 16 by 16 polariton matrix multiplier running at room temperature. IBM Research has licensed the underlying fabrication technique and is testing integration with existing silicon photonics foundry runs.
Step 1: Read the open access paper at https://www.nature.com/articles/s41566-024-01457-3 to extract device parameters. Step 2: Contact the authors via the lab website to request design files for the polariton gate layout. Step 3: Submit the layout to a multi project wafer run at AIM Photonics to obtain test chips within six months.