Penn Physicists Fuse Light and Matter to Cut AI Power Draw

Researchers at the University of Pennsylvania built a hybrid light-matter quasiparticle called a polariton that replaces selected electronic logic gates with photonic operations. The device performs matrix multiplications at near-light speed while consuming roughly one-tenth the energy of equivalent transistor circuits. Tests on a 4-by-4 photonic array showed inference latency dropping from 12 nanoseconds to 0.9 nanoseconds per operation.

This work shows that moving select compute steps from electrons to photons can slash both latency and wattage without sacrificing numerical precision. Readers should therefore audit their training and inference pipelines for matrix-heavy layers that could migrate to photonic accelerators once commercial boards appear. The principle is simple: measure joules per FLOP before defaulting to silicon-only stacks.

The Penn Electrical and Systems Engineering group, led by Professor Ritesh Agarwal, has taped out a 64-polariton prototype on a silicon-nitride platform that sustains 200 TOPS per watt, a 9x gain over their prior electronic test chip.